page . 1 rev.0.4-sep.7.2009 pjsmda05 series preliminary features ? 350w power dissipation (8/20 s waveform) ? low leakage current, maximum of 5 a at rated voltage ? very low clamping voltage ? iec61000-4-2 esd 20kv air,15kv contact compliance ? in compliance with eu rohs 2002/95/ec directives mechanical data ? case: soic-08,molded plastic over passivated junction ? terminals: solderable per mil-std-750, method 2026 ? approx. weight: 0.079 grams ? mounting position : any applications ? rs-232c or rs-422 communication ports ? gpib/ieee 485 ports ? portable instrumentation quad tvs/zener array for esd and latch-up protection this quad tvs/zener array family have been designed to protect sensitive equipment against esd and to prevent latch-up events in cmos circuity operating at 5v,12v,15v and 24v. this tvs array offers an integrated sloution to protect up to 4 data lines where the board space is a premium. maximum ratings (per device) fig.67 1 234 8765 rating symbol value units peak pulse power (8/20 s waveform) p pp 350 w esd voltage (hbm) per mil-std-883c v esd >25 kv operating temperature range t j -50 to +150 o c storage temperature range t stg -50 to +150 o c
page . 2 rev.0.4-sep.7.2009 pjsmda05 series preliminary electrical characteristics (per device) t j = 25c pjsmda05 marking da5 parameter symbol condition min. typ. max. units reverse stand-off voltage v rwm --5 v reverse breakdown voltage v br i br =1ma 6 - - v reverse leakage current i r v r =5v - - 5 a clamping voltage (8/20 s) v c i pp =5a - - 9.8 v clamping voltage (8/20 s) v c i pp =24a - - 13 v off state junction capacitance c j 0 vdc bias f=1mh z - 400 500 pf off state junction capacitance c j 5 vdc bias f=1mh z - 200 250 pf pjsmda12 marking da2 parameter symbol condition min. typ. max. units reverse stand-off voltage v rwm --12 v reverse breakdown voltage v br i br =1ma 13.3 - - v reverse leakage current i r v r =5v - - 5 a clamping voltage (8/20 s) v c i pp =5a - - 20 v clamping voltage (8/20 s) v c i pp =15a - - 25 v off state junction capacitance c j 0 vdc bias f=1mh z - - 300 pf pjsmda15 marking daa parameter symbol condition min. typ. max. units reverse stand-off voltage v rwm --15 v reverse breakdown voltage v br i br =1ma 16.7 - - v reverse leakage current i r v r =5v - - 5 a clamping voltage (8/20 s) v c i pp =5a - - 24 v clamping voltage (8/20 s) v c i pp =12a - - 29 v off state junction capacitance c j 0 vdc bias f=1mh z - - 200 pf pjsmda24 marking da4 parameter symbol condition min. typ. max. units reverse stand-off voltage v rwm --24 v reverse breakdown voltage v br i br =1ma 26.7 - - v reverse leakage current i r v r =5v - - 5 a clamping voltage (8/20 s) v c i pp =5a - - 40 v clamping voltage (8/20 s) v c i pp =8a - - 44 v off state junction capacitance c j 0 vdc bias f=1mh z - - 120 pf
page . 3 rev.0.4-sep.7.2009 pjsmda05 series preliminary 500 400 300 200 100 0 pjsmda05 pjsmda12 pjsmda15 pjsmda24 0 5 10 15 20 25 typical characteristics t j = 25c unless otherwise noted
page . 4 rev.0.4-sep.7.2009 mounting pad layout ? packing information t/r - 3k per 13" plastic reel order information legal statement copyright panjit international, inc 2009 the information presented in this document is believed to be accurate and reliable. the specifications and information herein are subject to change without notice. pan jit makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. pan jit products are not authorized for use in life support devices or systems. pan jit does not convey any license under its patent rights or rights of others. pjsmda05 series preliminary
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